Hantro 7280 Video Encoder

Multi-format configurable hardware (RTL) design for low powered multimedia SOCs

Ultra low power high performance SXGA (1280x1024) encoder IP core
The Hantro 7280 Multi-format encoder core processes up to 1280 x 1024 resolution video at 30 frames per second. Designed for chipsets intended for devices with very lower power requirements such as: portable video cameras, mobile phones, remote security cameras, laptops and web cams etc. the encoder combines ultra low power consumption with high resolution and broad format support.

Capable of encoding 30fps 720p HD resolution H.264 video in only 180MHz clock frequency, the 7280 brings extremely high performance to 65nm and 90nm low power chipsets.

The 7280 also incorporates a proprietary indexed full search motion estimation algorithm which further reduces clock requirement without affecting video quality.

Design innovations optimize power, silicon utilization and integration

• Format and pre-processing configuration: optimize silicon area by selecting only the formats you need for your SOC design. Sizes start from 0.19mm² / 139k gates.
  
• Performance configuration: choose internal memory size according to your resolution requirement - from QCIF to SXGA.
  
• Share internal memories with decoder core: combine with the Hantro 7190 or Hantro 8190 for a full codec solution.
• Target SoC configuration: choose the bus protocol interface from AHB, AXI and OCP.
• Easy application development: simple application programming interface with OpenMax, Symbian MDF and DirectShow® options available.

Supported formats and resolutions

7280 Hardware Encoder Block Diagram

Proprietary Video Stabilization  Technology 

The Hantro 7280 incorporates unique technology to improve the observed image quality of captured video by counteracting the effects of camera shake. When the feature is enables, each frame or raw video is analyzed and the undesired movement is removed by cropping and repositioning the frame (illustrated below). The level of stabilization can be configured by defining the size of area to be cropped.

In addition to improving perceived image quality, compression efficiency is also increase as the frame analysis and cropping are done prior to encoding.

• RTL source code (VHDL or Verilog) with an RTL test bench and test data.
• ANSI C source code for hardware drivers with software test bench and test data.
• Technical documentation; hardware and software integration guides and application programming interface (API) manuals.